The present disclosure relates generally an integrated circuit device and, more particularly, to method for gap filling in a gate last process.
As technology nodes shrink, in some IC designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. Providing metal gate structures (e.g., including a metal gate electrode rather than polysilicon) offers one solution. One process of forming a metal gate stack is termed “gate last” process in which the final gate stack is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high dielectric constant (high-k) gate insulator layers are also used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a typical gate oxide used in larger technology nodes.
There are challenges to implement such features and processes in CMOS fabrication however. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, in a “gate last” fabrication process, voids may be generated during deposition of an inter-layer dielectric (ILD) for gap filling. Also, controlling the gate height during a chemical mechanical polishing (CMP) on the ILD is difficult. Therefore, what is needed is a new and improved device and method of gate formation.